The invention described herein relates generally to semiconductor chip manufacturing processes. In particular, the invention relates to improved method and structure for forming solder layers on integrated circuit package electrical contacts.
The present invention relates generally to the bulk packaging of integrated circuits. More particularly, the invention relates to the use of leadless packaging processes and designs that utilize a conductive substrate.
A leadless leadframe package (LLP) is a relatively new integrated circuit package design that contemplates the use of a metal (typically copper) leadframe type substrate structure in the formation of a chip scale package (CSP). As illustrated in FIGS. 1(a)-1(c), in typical leadless leadframe packages, a copper leadframe strip or panel 101 is patterned (typically by stamping or etching) to define a plurality of arrays 103 of chip substrate features 105. Each chip substrate feature 105 includes a die attach pad 107 and a plurality of contacts 109 (also known as lead pads or leads) disposed about their associated die attach pad 107. Very fine tie bars 111 can be used to support the die attach pads 107 and leads 109.
During assembly, integrated circuit dies are attached to the respective die attach pads and conventional wire bonding is used to electrically couple bond pads on each die to their associated leads 109 on the leadframe strip 101. After the wire bonding, a plastic cap is molded over the top surface of each array 103 of wire bonded integrated circuit dies.
In order to enhance electrical conduction properties and facilitate attachment of singulated integrated circuit dies to a substrate (e.g., a printed circuit board (PCB)), a back side surface (not depicted in these views) of the leads 109 and the die attach pads 107 are electro-plated with a solder material. The integrated circuit dies are then singulated and tested using conventional sawing and testing techniques.
FIG. 2 illustrates a typical resulting leadless leadframe package after singulation. The die attach pad 107 supports an integrated circuit die 120 which is electrically connected to its associated leads 109 by bonding wires 122. A plastic cap 125 encapsulates the die 120 and bonding wires 122 and fills the gaps between the die attach pad 107 and the contacts 109 thereby serving to hold the contacts in place. A layer of solder material 126 about 8-11 xcexcm (micron) thick is electro-plated onto the backside surface of the leads 109 and the die attach pads 107.
It should be appreciated that during singulation, the tie bars 111 are cut and therefore the only material holding the contacts 109 in place is the molding material. The resulting packaged chip can then be surface mounted on a printed circuit board (PCB) or other substrate using conventional techniques.
During die attachment to PCBs, a certain fraction of such attachment processes fails to adequately attach the dies to the PCB. Such dies must be removed and xe2x80x9creworkedxe2x80x9d to facilitate reattachment. Conventional rework processes utilize a much thicker layer of solder material in order to effectively attach the reworked die to a PCB. Layers of solder material used to accomplish the rework process range from 30-90 xcexcm thick. In conventional processes, the application of this new, thicker solder layer has proven troublesome. The ability to uniformly and repeatedly apply solder materials having appropriate thicknesses to reworked integrated circuit dies has proved an elusive goal. Therefore, continuing efforts are being made to further improve the package structure and processing techniques so that thicker solder layers can be formed, production costs can be reduced, production efficiency can be increased, and/or production yields can be improved.
To address the foregoing issues, as well as others, and according to the purpose of the present invention, an improved method of forming solder layers on a integrated circuit package is disclosed.
One embodiment of the invention comprises a substrate sheet used for forming integrated circuit packages. The substrate sheet is formed of a conducting material having a first surface and a second surface. The substrate sheet is patterned to define a plurality of device features, including a die attach pad and a plurality of associated lead pads. The first surface of the die attach pad is configured to receive a semiconductor integrated circuit die. The second surface of the die attach pad has formed thereon a pattern of mesas configured such that each mesa has a surface area of approximately the same size as the lead pad surface area.
Another embodiment discloses an integrated circuit package having an integrated circuit die attached to the top surface of a die attach pad and electrically interconnected with a plurality of associated lead pads. The combination is encapsulated by a cap such that a bottom surface of the die attach pad and a bottom surface of the lead pads are exposed. The exposed bottom surface of the die attach pad includes a plurality of mesas arranged on the bottom surface of the die attach pad. Each of the mesas is configured having a surface area of approximately the same size as a surface area of a lead pad. A contact layer of reflowable material is formed on the exposed tops of the mesas and on the exposed bottom surfaces of the plurality of lead pads.
Another embodiment discloses a method of packaging integrated circuits. The method includes providing a substrate sheet formed of a conducting material having a first surface and a second surface. The substrate sheet is subjected to a first patterning to define a multiplicity of device areas, each device area including a die attach pad and a plurality of associated lead pads. A second patterning of the second surface of the die attach pads is conducted to generate a pattern of grooves such that the grooves define a multiplicity of mesas on the second surface of the die attach pad. Each of the mesas having a surface area of approximately the same size as the surface area of one of the lead pads. In another embodiment, the foregoing method includes the further steps of attaching a semiconductor die to the first surface of each die attach pad and electrically connecting the die to its associated lead pads. A capping layer is then molded over the device areas to encapsulate the semiconductor dies and to fill in at least some of the grooves. A contact layer of reflowable material is formed on the tops of the mesas and on the exposed surfaces of the lead pads. The substrate sheet is subsequently singulated into individual integrated circuit packages.
Numerous specific implementations of the above-described embodiments are also described. These and other aspects of the invention are described in the following xe2x80x9cDetailed Description.xe2x80x9d